By way of receiver gain control background, each of the receiver tributaries (XI:XQ:YI:YQ) typically has its own independent AGC loop to control its gain to maintain a constant radio frequency (RF) power (PADC) at the high speed analog-to-digital converter (ADC) input. An independent AGC loop per receiver tributary works fine for symmetrical constellations, where the power on the I-axis and the power on the Q-axis are always the same regardless of rotation, e.g., for a quadrature phase shift keying (QPSK) signal of equal power for all four constellations.
As illustrated in FIG. 1, because the distance from the origin to each constellation is the same, the power on each axis is the same.PAxis,1=PAxis,Q=(A cos θ)2+(A sin θ)2=A2  (1)Thus, the powers on the I and Q axes are constant independent of θ. This is true for all symmetrical constellations.
As illustrated in FIG. 2, all commercially available dual (illustrated) and quad transimpedance amplifiers (TIAs) for coherent receivers utilize such independent AGC loops. Here, for the coherent receiver 10, the TIAs 12 are each coupled to their own ADC 14 and utilize their own AGC loop 16. For each channel, DET 18 is the power detector of the TIA RF output, VDET 20 is the detector output voltage, VREF 22 is the reference voltage of the AGC loop 16, Σ 24 is the voltage summing (error=VREF−V DET), the loop filter 26 is the integrator loop (VGC=KLF∫error dt), and PADC,ch 28 is the RF power at the ADC input. Again, the gain of each channel is controlled by its own AGC loop 16, and the AGC loop 16 of each channel locks the RF power to the ADC 14 to a constant value.
For constellations that are single-axis, e.g., binary phase shift keying (BPSK), quaternary amplitude shift keying (4ASK), and constellations that are otherwise engineered to be asymmetrical, an independent AGC loop per tributary is not desirable. Such constellations are constantly rotating. The angular speed of rotation depends on the intermodulation frequency (IF) between the transmitter (Tx) and the receiver (Rx). When the IF falls within the tracking bandwidth of the AGC loop, the two or four independent AGCs will act to re-normalize the I and Q power imbalance and the received symbols at the corresponding ADC will appear to have symmetrical projections to the downstream digital signal processor (DSP). This re-normalization destroys the integrity of BPSK and 4ASK. It also removes the benefits of the engineered asymmetrical constellation.
The objective is to maintain the signature of the I and Q power imbalance or ratio at the ADC. Instead of locking the RF power at the I-axis ADC and the Q-axis ADC individually with two AGC loops, one AGC loop will be used to lock the SUM of the RF power at the I-axis and Q-axis ADCs.
As illustrated in FIG. 3, the distance from the origin to each pair of constellations is different. Therefore, the power on the I-axis and the Q-axis is different.PAxis,1=(A cos θ)2+(B sin θ)2; PAxis,Q=(A sin θ)2+(B cos θ)2  (2)However, adding the power of the I-axis and the Q-axis together, the total power constant is independent of θ.PAxis,I+PAxis,Q=(A cos θ)2+(B sin θ)2+(A sin θ)2+(B cos θ)2  (3)PAxis,I+PAxis,Q=A2+B2  (4)
Thus, again, all commercially available TIAs are designed with dedicated AGC loops per tributary. Many TIAs do not have integrated AGC loops, but utilize external AGC loops to set their gain. Typically, these external AGC loops are digital.
Commercially available TIAs having dedicated AGC loops per tributary typically have bandwidths from tens of KHz to MHz. Therefore, when an asymmetrical modulated signal is applied, the AGC loop can track the IF and re-normalize the associated constellation. Particularly if end-to-end laser frequency control is active, there is a high probability that IF≈0. Alternatively, one can set the AGC bandwidth to a very, very low bandwidth, e.g., BWAGC<1 Hz, so that the AGC loops do not track low-frequency IF. However, this limits the capability of the AGC loops to track optical power transients.
Current TIAs with external AGC circuits often have a digital AGC loop integrated in a field-programmable gate array (FPGA), for example. These digital AGC loops may have the functionality to control the I and Q gains from two independent AGC loops or from one common AGC loop. These current digital AGC solutions are, however, not suitable for use in high-integration pluggable coherent modems. There are many interconnects between the DSP-to-TIA chips and many external components that limit integration and introduce noise. Furthermore, the digital AGC loop drives complexity to the DSP chip. An integrated analog AGC loop in the TIA is thus a more suitable solution for pluggable coherent modems.
A conventional external digital AGC circuit 30 is illustrated in FIG. 4. With the AGC loop implemented in the TIA 12 instead, this enables greater integration (area, power, etc.) and more flexible hardware/technology migration (DSP evolution, commercial DSP usage, etc.) without re-designing and re-verifying existing AGC loops in the FPGA or application-specific integrated circuit (ASIC).